Along with the evolution in the manufacturing technology of semiconductor devices, the functional density of the semiconductor devices has increased with the decrease of device sizes to achieve higher integration density of the semiconductor devices. As a result, demands to packaging technology are becoming severe under conditions of decreases in size and increases in density of the semiconductor devices. In recent years, the demands to the smaller electronic devices have increased, and innovative packaging technology is required.
Generally, several devices are fabricated in a wafer, and a dicing process is performed to separate these devices into individual chips. These chips are placed on a carrier substrate, and a packaging process is performed to integrate multiple chips into one package. However, these chips suffer vibration when being placed on the carrier substrate, and problems of disconnection and fracture may easily occur to the chips, which decreases the yield of the package. In addition, extra costs for the carrier substrate further decrease efficiency of the packaging process. Therefore, a novel packaging structure and a manufacturing process thereof are necessary to solve problems mentioned above.